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Intel® SHG2 DP Server Board Technical Product Specification Error Reporting and Handling
Revision 1.0 Intel Order Number C11343-001
35
6. Error Reporting and Handling
This section defines how errors are handled by the system BIOS on the Intel SHG2 server
board. Also discussed is the role of BIOS in error handling, and the interaction between the
BIOS, platform hardware, and server management firmware with regard to error handling. In
addition, error-logging techniques are described, and beep codes for errors are defined.
6.1 Error Sources and Types
One of the major requirements of server management is to correctly and consistently handle
system errors. System errors, which can be disabled and enabled individually or as a group,
can be categorized as follows:
•
PCI bus
•
Memory correctable- and uncorrectable errors
•
Sensors
•
Processor internal error, bus/address error, thermal trip error, temperatures and
voltages, and assisted gunning transceiver logic (AGTL+) voltage levels
Sensors are managed by the BMC. The BMC is capable of receiving event messages from
individual sensors and logging system events.
6.2 Handling and Logging System Errors
This section describes actions taken by the SMI handler with respect to the various categories
of system errors. It covers the events logged by the BIOS, and the format of data bytes
associated with those events. The BIOS is responsible for monitoring and logging certain
system events. The BIOS sends a platform event message to BMC to log the event. Some of
the errors, such as processor failure, are logged during early POST, and not through the SMI
handler.
6.2.1 Logging Format Conventions
The BIOS complies with the Intelligent Platform Management Interface Specification, Revision
1.5. The BIOS always uses system software ID within the range 00h-1Fh to log errors. As a
result, the generator ID byte is an odd number in the range 01h-3fh. OEM user binary should
use software IDs of 1. The software ID allows external software to find the origin of the event
message.
- SHG2 DP Server Board 1
- Revision History 2
- Disclaimers 2
- Table of Contents 3
- List of Figures 8
- List of Tables 9
- 1. Introduction 13
- 2. Processor and Chipset 18
- 2.2.5 CMIC-LE 20
- 2.3 Memory Subsystem 21
- DIMM 2A, DIMM 2B 2 3, 4 22
- DIMM 3A, DIMM 3B 3 5, 6 22
- Memory DIMM DIMM PAIR Row 22
- DIMM 1A, DIMM 1B 1 1, 2 22
- 2.3.3 CIOB-X2 23
- 2.4 CSB5 South Bridge 23
- 2.4.1 PCI Interface 24
- 2.4.3 USB Interface 24
- 2.4.4 BIOS Flash 24
- 3.1 Overview 30
- 3.3.1 Device IDs (IDSEL) 31
- Baseboard Signals Device 32
- 3.5.1 Device IDs (IDSEL) 33
- 3.5.4 Video Controller 34
- 3.6 Interrupt Routing 35
- 3.6.2 IRQ scan for PCIIRQ 38
- 66/133 MHz 40
- 5.2 System Reset Control 43
- 5.2.2 Hard Reset 44
- 5.2.3 Soft Reset 44
- 6.1 Error Sources and Types 47
- Specification.) 48
- 6.4 Firmware (BMC) 50
- System RAM error 57
- 7.1 Hardware Configuration 60
- 8. Connections 62
- 8.3 SCSI Connectors 64
- 8.4 Floppy Connector 65
- CN31 [Key-H] 65
- 8.5 IDE Connectors 66
- 8.6 Front Panel Interface 67
- CN37 [Key-E] 67
- 8.7 Processor Connector 68
- 8.8.1 ICMB Connector 72
- 8.8.2 Auxiliary I 72
- C* Connector 72
- (FAN1 through FAN8) 73
- 8.9.1 Fan Connector Pin-out 75
- Pin Signal USB Connector 77
- 8.10.3 Serial Ports 78
- 8.10.4 Parallel Port 79
- 8.10.5 Video Port 80
- 8.10.6 Ethernet Connectors 80
- Interface 82
- Definition 82
- 9. General Specifications 84
- 9.3.1 Power Consumption 85
- Conformity) 93
- Conformity 93
- 11.2.4 BSMI (Taiwan) 93
- Appendix A: Glossary 95
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